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VSP2000 数据表(PDF) 9 Page - Burr-Brown (TI) |
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VSP2000 数据表(HTML) 9 Page - Burr-Brown (TI) |
9 / 12 page ® VSP2000 9 BLACK LEVEL AUTO-ZERO LOOP The black level auto-zero loop amplifies the difference between the output of the output amplifier and a reference signal during the dummy pixel interval. This difference signal is amplified and fed back into the output amplifier to correct the offset. In doing so, the output level of the entire CCD channel can be controlled to be approximately –FS + 32LSBs under zero signal conditions. The black level auto- zero loop is activated by the OB timing signal. Figure 5 shows a block diagram of the black level auto-zero loop. The loop time constant is given by: A/D CONVERTER The A/D converter utilizes a pipline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The A/D converter circuitry includes a reference circuit that provides bias voltages for the entire system. DECOUPLING AND GROUNDING CONSIDERATIONS The VSP2000 has several supply pins, one of which is dedicated to supply only the digital output driver (pin 17, DVDD1). The remaining supply pins are not, as is often the case, divided into analog and digital supply pins since they are internally connected on the chip. For this reason, it is recommended that the VSP2000 be treated as an analog component and to power if from the analog supply only. Digital supply lines often carry high levels of wide band noise which can couple back into the VSP2000 and limit performance. Figure 6 shows the recommended decoupling scheme for the VSP2000. In most cases, 0.1 µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual pin. Therefore, they should be located as close as possible to the pins. In addition, one larger capacitor (1 µF to 22µF) should be placed on the PC board in proxim- ity of the VSP2000. DEMONSTRATION BOARD A demonstration board, DEM-VSP2000, is available to assist in the inital evaluation of the circuit performance using the VSP2000. The schematic and board layout of the DEM-VSP2000 are shown in Figure 6 and Figures 7a through 7d, respectively. T = C (GM) (D) where C is the external filter capacitance applied to pin 24 (C), G M is .001Ω and D is the duty cycle of the time that the black level auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the black level auto-zero loop is activated by the OB signal that happens once during each horizontal line interval. OB To ADS 32LSB Error Amplifier GM From VCA C C FIGURE 5. Black Level Auto-Zero Loop. |
类似零件编号 - VSP2000 |
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类似说明 - VSP2000 |
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