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DRV8301-Q1 Datasheet(数据表) 10 Page - Texas Instruments

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部件型号  DRV8301-Q1
说明  AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DRV8301-Q1 Datasheet(HTML) 10 Page - Texas Instruments

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DRV8301-Q1
SLOS842 – SEPTEMBER 2013
www.ti.com
CURRENT SHUNT AMPLIFIER CHARACTERISTICS
TC = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G1
Gain option 1
Tc = -40°C-125°C
9.5
10
10.5
V/V
G2
Gain option 2
Tc = -40°C-125°C
18
20
21
V/V
G3
Gain Option 3
Tc = -40°C-125°C
38
40
42
V/V
G4
Gain Option 4
Tc = -40°C-125°C
75
80
85
V/V
Tsettling
Settling time to 1%
Tc = 0-60°C, G = 10, Vstep = 2 V
300
ns
Tsettling
Settling time to 1%
Tc = 0-60°C, G = 20, Vstep = 2 V
600
ns
Tsettling
Settling time to 1%
Tc = 0-60°C, G = 40, Vstep = 2 V
1.2
µs
Tsettling
Settling time to 1%
Tc = 0-60°C, G = 80, Vstep = 2 V
2.4
µs
Vswing
Output swing linear range
0.3
5.7
V
Slew Rate
G = 10
10
V/µs
DC_offset
Offset error RTI
G = 10 with input shorted
4
mV
Drift_offset
Offset drift RTI
10
µV/C
Ibias
Input bias current
100
µA
Vin_com
Common input mode range
–0.15
0.15
V
Vin_dif
Differential input range
–0.3
0.3
V
Vo_bias
Output bias
With zero input current, Vref up to 6 V
–0.5%
0.5×Vref
0.5%
V
Overall CMRR with gain resistor
CMRR_OV
CMRR at DC, gain = 10
70
85
dB
mismatch
BUCK CONVERTER CHARACTERISTICS
TC = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VUVLO
Internal undervoltage lockout threshold
No voltage hysteresis, rising and falling
2.5
V
ISD(PVDD2)
Shutdown supply current
EN = 0 V, 25°C, 3.5 V
≤ VIN ≤ 60 V
1.3
4
µA
INON_SW(PVDD2) Operating: nonswitching supply current
VSENSE = 0.83 V, VIN = 12 V
116
136
µA
No voltage hysteresis, rising and falling,
VEN_BUCK
Enable threshold voltage
0.9
1.25
1.55
V
25°C
RDS_ON
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
m
ILIM
Current limit threshold
VIN = 12 V, TJ = 25°C
1.8
2.7
A
Fsw
Switching frequency
RT = 200 k
450
581
720
kHz
VSENSE falling
92%
VSENSE rising
94%
PWRGD
VSENSE threshold
VSENSE rising
109%
VSENSE falling
107%
Hysteresis
VSENSE falling
2%
VSENSE = VREF, V(PWRGD) = 5.5 V,
Output high leakage
10
nA
25°C
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
50
SPI CHARACTERISTICS (Slave Mode Only)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI ready after EN_GATE transitions to
tSPI_READY
PVDD > 6 V
5
10
ms
HIGH
tCLK
Minimum SPI clock period
100
ns
tCLKH
Clock high time
40
tCLKL
Clock low time
40
tSU_SDI
SDI input data setup time
20
ns
10
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DRV8301-Q1




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