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DRV8301-Q1 Datasheet(数据表) 6 Page - Texas Instruments

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部件型号  DRV8301-Q1
说明  AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DRV8301-Q1 Datasheet(HTML) 6 Page - Texas Instruments

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DRV8301-Q1
SLOS842 – SEPTEMBER 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE
UNITS
MIN
MAX
PVDD
Supply voltage range including transient
Relative to PGND
–0.3
70
V
PVDDRAMP
Maximum supply voltage ramp rate
Voltage rising up to PVDDMAX
1
V/µs
VPGND
Maximum voltage between PGND and GND
±0.3
V
IIN_MAX
Maximum current, all digital and analog input pins except FAULT and OCTW pins
±1
mA
IIN_OD_MAX
Maximum sinking current for open drain pins (FAULT and OCTW Pins)
7
mA
VOPA_IN
Voltage range for SPx and SNx pins
±0.6
V
VLOGIC
Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,
-0.3
7
V
INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)
VGVDD
Maximum voltage for GVDD Pin
13.2
V
VAVDD
Maximum voltage for AVDD Pin
8
V
VDVDD
Maximum voltage for DVDD Pin
3.6
V
VVDD_SPI
Maximum voltage for VDD_SPI Pin
7
V
VSDO
Maximum voltage for SDO Pin
VDD_SPI +0.3
V
VREF
Maximum reference voltage for current amplifier
7
V
IREF
Maximum current for REF Pin
100
µA
TJ
Maximum operating junction temperature range
–40
150
°C
TSTORAGE
Storage temperature range
–55
150
°C
Capacitive discharge model
Per AEC-Q100
Human body model
Per AEC-Q100
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
DRV8301-Q1
THERMAL METRIC(1)
DCA
UNITS
56 PINS
θJA
Junction-to-ambient thermal resistance(2)
30.3
θJCtop
Junction-to-case (top) thermal resistance(3)
33.5
θJB
Junction-to-board thermal resistance(4)
17.5
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.9
ψJB
Junction-to-board characterization parameter(6)
7.2
θJCbot
Junction-to-case (bottom) thermal resistance(7)
0.9
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Copyright © 2013, Texas Instruments Incorporated
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