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DRV8301-Q1 Datasheet(数据表) 3 Page - Texas Instruments

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部件型号  DRV8301-Q1
说明  AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DRV8301-Q1 Datasheet(HTML) 3 Page - Texas Instruments

 
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DRV8301-Q1
www.ti.com
SLOS842 – SEPTEMBER 2013
PIN FUNCTIONS
PIN
I/O(1)
DESCRIPTION
NAME
NO.
RT_CLK
1
I
Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with
very short trace to reduce the potential clock jitter due to noise.
COMP
2
O
Buck error amplifier output and input to the output switch current comparator.
VSENSE
3
I
Buck output voltage sense pin. Inverting node of error amplifier.
PWRGD
4
I
An open drain output with external pull-up resistor required. Asserts low if buck output voltage is low
due to thermal shutdown, dropout, over-voltage, or EN_BUCK shut down
OCTW
5
O
Over current or/and over temperature warning indicator. This output is open drain with external pull-up
resistor required. Programmable output mode via SPI registers.
FAULT
6
O
Fault report indicator. This output is open drain with external pull-up resistor required.
DTC
7
I
Dead-time adjustment with external resistor to GND
SCS
8
I
SPI chip select
SDI
9
I
SPI input
SDO
10
O
SPI output
SCLK
11
I
SPI clock signal
DC_CAL
12
I
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
calibration can be done through external microcontroller.
GVDD
13
P
Internal gate driver voltage regulator. GVDD cap should connect to GND
CP1
14
P
Charge pump pin 1, ceramic cap should be used between CP1 and CP2
CP2
15
P
Charge pump pin 2, ceramic cap should be used between CP1 and CP2
EN_GATE
16
I
Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin.
INH_A
17
I
PWM Input signal (high side), half-bridge A
INL_A
18
I
PWM Input signal (low side), half-bridge A
INH_B
19
I
PWM Input signal (high side), half-bridge B
INL_B
20
I
PWM Input signal (low side), half-bridge B
INH_C
21
I
PWM Input signal (high side), half-bridge C
INL_C
22
I
PWM Input signal (low side), half-bridge C
DVDD
23
P
Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified
to drive external circuitry.
REF
24
I
Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the
voltage set on this pin. Connect to ADC reference in microcontroller.
SO1
25
O
Output of current amplifier 1
SO2
26
O
Output of current amplifier 2
AVDD
27
P
Internal 6V supply voltage, AVDD cap should always be installed and connected to AGND. This is an
output, but not specified to drive external circuitry.
AGND
28
P
Analog ground pin
PVDD1
29
P
Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is
independent of buck power supply, PVDD2. PVDD1 cap should connect to GND
SP2
30
I
Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
SN2
31
I
Input of current amplifier 2 (connecting to negative input of amplifier).
SP1
32
I
Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
SN1
33
I
Input of current amplifier 1 (connecting to negative input of amplifier).
SL_C
34
I
Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and
SH_C.
GL_C
35
O
Gate drive output for Low-Side MOSFET, half-bridge C
SH_C
36
I
High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and
PVDD1.
GH_C
37
O
Gate drive output for High-Side MOSFET, half-bridge C
(1)
KEY: I =Input, O = Output, P = Power
Copyright © 2013, Texas Instruments Incorporated
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