数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF HTML

DRV8301-Q1 Datasheet(数据表) 19 Page - Texas Instruments

Click here to check the latest version.
部件型号  DRV8301-Q1
说明  AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS
下载  28 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 

DRV8301-Q1 Datasheet(HTML) 19 Page - Texas Instruments

Zoom Inzoom in Zoom Outzoom out
 19 page
background image
DRV8301-Q1
www.ti.com
SLOS842 – SEPTEMBER 2013
SPI output data response word is 16-bit long, and its content depends on the given SPI command (SPI Control
Word) in the previous cycle. When a SPI Control Word is shifted in, the SPI Response Word (that is shifted out
during the same transition time) is the response to the previous SPI Command (shift in SPI Control Word "N" and
shift out SPI Response Word "N-1").
Therefore, each SPI Control / Response pair requires two full 16-bit shift cycles to complete.
Table 3. SPI Input Data Control Word Format
R/W
Address
Data
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 4. SPI Output Data Response Word Format
R/W
Data
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
F0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI Control and Status Registers
Read / Write Bit
The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1,
input data is a read command, and the register value will send out on the same word cycle from SDO from D10
to D0.
Address Bits
Table 5. Register Address
Register
Register Type
Address [A3..A0]
Description
Read and Write Access
Name
Status
Report occurred faults after previous
0
0
0
0
R (auto reset to default values after read)
Register 1
reading
Status
Device ID: R
Register
Status
Device ID and report occurred faults
0
0
0
1
Fault report: R (auto reset to default
Register 2
after previous reading
values after read)
Control
0
0
1
0
R/W
Register 1
Control
Register
Control
0
0
1
1
R/W
Register 2
SPI Data Bits
Status Registers
Table 6. Status Register 1 (Address: 0x00) (all default values are zero)
Register
Address
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Status
0x00
FAULT
GVDD_UV
PVDD_UV
OTSD
OTW
FETHA_OC
FETLA_OC
FETHB_OC
FETLB_OC
FETHC_OC
FETLC_OC
Register 1
Table 7. Status Register 2 (Address: 0x01) (all default values are zero)
Address
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0x01
Status
GVDD_OV
Device ID
Register 2
0
0
0
0
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DRV8301-Q1




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


数据表 下载




链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl