AD7810

–6–

REV. B

CIRCUIT DESCRIPTION

Converter Operation

The AD7810 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. The ADC

ures 4 and 5 below show simplified schematics of the ADC.

Figure 4 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A; the comparator is held in a

balanced condition; and the sampling capacitor acquires the

CHARGE

REDISTRIBUTION

DAC

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

ACQUISITION

PHASE

SW2

A

SW1

B

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 5), SW2 will

open and SW1 will move to Position B, causing the comparator

to become unbalanced. The control logic and the charge redis-

tribution DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. Figure 11 shows the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW2

A

SW1

B

Figure 5. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7810. The

serial interface is implemented using two wires; the rising edge

of CONVST enables the serial interface—see Serial Interface

mode, i.e., power-down. A rising edge on the CONVST input

will cause the part to power up—see Operating Modes. If power

consumption is of concern, the automatic power-down at the

end of a conversion should be used to improve power perfor-

mance. See Power vs. Throughput Rate section of the data sheet.

SCLK

AGND

CONVST

SUPPLY

2.7V TO 5.5V

INPUT

AD7810

0.1 F

10 F

TWO WIRE

SERIAL

INTERFACE

C/ P

Figure 6. Typical Connection Diagram

Analog Input

Figure 7 shows an equivalent circuit of the analog input struc-

ture of the AD7810. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 200 mV. This will cause these diodes to become

forward biased and start conducting current into the substrate.

The maximum current these diodes can conduct without caus-

ing irreversible damage to the part is 20 mA. The capacitor C2

is typically about 4 pF and can be primarily attributed to pin

capacitance. The resistor R1 is a lumped component made up of

the on resistance of a multiplexer and a switch. This resistor is

typically about 125

Ω. The capacitor C1 is the ADC sampling

capacitor and has a capacitance of 3.5 pF.

C1

3.5pF

R1

125

D2

D1

C2

4pF

CONVERT PHASE – SWITCH OPEN

ACQUISITION PHASE – SWITCH CLOSED

Figure 7. Equivalent Analog Input Circuit

The analog input of the AD7810 is made up of a pseudo differ-

(see Figure 8). This input scheme can be used to remove offsets

that exist in a system. For example, if a system had an offset of

It is only possible to offset the input span when the reference

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW2

CHARGE

REDISTRIBUTION

DAC

Figure 8. Pseudo Differential Input Scheme