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AD7243AQ 数据表(PDF) 7 Page - Analog Devices |
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AD7243AQ 数据表(HTML) 7 Page - Analog Devices |
7 / 12 page REV. A –7– AD7243 Although 16 bits of data are clocked into the input register, only the latter 12 bits get transferred into the DAC latch. The first 4 bits in the 16 bit stream are don’t cares since their value does not affect the DAC latch data. Therefore, the data format is 4 don’t cares followed by the 12-bit data word with the LSB as the last bit in the serial stream. There are two ways in which the DAC latch and hence the ana- log output may be updated. The status of the LDAC input is examined after SYNC is taken low. Depending on its status, one of two update modes is selected. If LDAC = 0, then the automatic update mode is selected. In this mode the DAC latch and analog output are updated auto- matically when the last bit in the serial data stream is clocked in. The update thus takes place on the sixteenth falling SCLK edge. If LDAC = 1, then the automatic update is disabled and the DAC latch is updated by taking LDAC low any time after the 16-bit data transfer is complete. The update now occurs on the falling edge of LDAC. Note that the LDAC input must be taken back high again before the next data transfer is initiated. Serial Data Loading Format (Daisy-Chain Mode) By connecting DCEN high the daisy-chain mode is enabled. This mode of operation is designed for multi-DAC systems where several AD7243s may be connected in cascade (see Fig- ure 16). In this mode the internal gating circuitry on SCLK is disabled, and a serial data output facility is enabled. The inter- nal gating signal is permanently active (low) so that the SCLK signal is continuously applied to the input shift register when SYNC is low. The data is clocked into the register on each fall- ing SCLK edge after SYNC going low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. By connecting this line to the SDIN input on the next AD7243 in the chain, a multi-DAC interface may be constructed. Sixteen SCLK pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input register. A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC latches with the lower 12 bits of data in each input register. All analog outputs are therefore up- dated simultaneously on the falling edge of LDAC. Clear Function ( CLR) The clear function bypasses the input shift register and loads the DAC Latch with all 0s. It is activated by taking CLR low. In all ranges except the Offset Binary bipolar range (–5 V to +5 V) the output voltage is reset to 0 V. In the offset binary bipolar range the output is set to –REFIN. The clear function is especially useful at power-up as it enables the output to be reset to a known state. SCLK DB11 (N) MSB DB0 (N) LSB * = DON'T CARE SDIN SYNC LDAC CLR DB0 (N) LSB SDO DB15 (N)* DB15* (N + 1) DB11 (N + 1) MSB DB0 (N + 1) LSB UNDEFINED DB15 (N)* DB11 (N) MSB t1 t2 t3 t5 t4 t11 t6 t7 t8 t9 t10 Figure 8. Timing Diagram (Daisy-Chain Mode) |
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类似说明 - AD7243AQ |
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