DP83620 datasheet(79/105 Pages) TI

部件名	DP83620

功能描述	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

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DP83620

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SNLS339C – JANUARY 2011 – REVISED APRIL 2013

10.1.12 MII Interrupt Status and Event Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be

set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 10-14. MII Interrupt Status and Event Control Register (MISR), address 0x12

Bit

Bit Name

Default

Description

15

LQ_INT

0, RO/COR

Link Quality Interrupt:

1 = Link Quality interrupt is pending and is cleared by the current read.

0 = No Link Quality interrupt pending.

14

ED_INT

0, RO/COR

Energy Detect Interrupt:

1 = Energy detect interrupt is pending and is cleared by the current read.

0 = No energy detect interrupt pending.

13

LINK_INT

0, RO/COR

Change of Link Status Interrupt:

1 = Change of link status interrupt is pending and is cleared by the current read.

0 = No change of link status interrupt pending.

12

SPD_INT

0, RO/COR

Change of Speed Status Interrupt:

Change of speed status interrupt.

1 = Speed status change interrupt is pending and is cleared by the current read.

0 = No speed status change interrupt pending.

11

DUP_INT

0, RO/COR

Change of Duplex Status Interrupt:

Change of duplex status interrupt. This function is selected if MICR[3] is set to 0.

1 = Duplex status change interrupt is pending and is cleared by the current read.

0 = No duplex status change interrupt pending.

10

ANC_INT

0, RO/COR

Auto-Negotiation Complete Interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared by the current

read.

0 = No Auto-negotiation complete interrupt pending.

9

FHF_INT

0, RO/COR

False Carrier Counter Half-Full Interrupt:

or

False carrier counter half-full interrupt. This function is selected if the PHYCR2[8:7]

CTR_INT

are both 0.

1 = False carrier counter half-full interrupt is pending and is cleared by the current

read.

0 = No false carrier counter half-full interrupt pending.

CTR Interrupt:

False carrier or Receive Error counter half-full interrupt. This function is selected if

either of PHYCR2[8:7] are set.

1 = False carrier or receive error counter half-full interrupt is pending and is cleared

by the current read.

0 = No false carrier or receive error counter half-full interrupt pending.

8

RHF_INT

0, RO/COR

Receive Error Counter half-full interrupt:

or

Receive error counter half-full interrupt. This function is selected if the

PCF_INT

PHYCR2[8:7] are both 0.

1 = Receive error counter half-full interrupt is pending and is cleared by the current

read.

0 = No receive error carrier counter half-full interrupt pending.

PCF Interrupt:

PHY Control Frame interrupt. This function is selected if either of PHYCR2[8:7] are

set.

1 = PHY Control Frame interrupt is pending and is cleared by the current read.

0 = No PHY Control Frame interrupt pending.

7

LQ_INT_EN

0, RW

Enable Interrupt on Link Quality Monitor event.

6

ED_INT_EN

0, RW

Enable Interrupt on energy detect event.

5

LINK_INT_EN

0, RW

Enable Interrupt on change of link status.

Register Block

79

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