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EP2SGX60D 数据表(PDF) 12 Page - Altera Corporation |
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EP2SGX60D 数据表(HTML) 12 Page - Altera Corporation |
12 / 36 page Page 12 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Figure 3 shows the schematic for configuring multiple FPGAs concurrently in the PS mode using an EPC device. Figure 3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8) Notes to Figure 3: (1) Connect VCC to the same supply voltage as the EPC device. (2) The nINIT_CONF pin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF or nCONFIG signal. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. (3) The EPC devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. (4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 10 on page 24. (5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1to F-A1, C-A15 to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP# to F- RP# , C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. (6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the appropriate device handbook. (7) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer to “Intel Flash-Based EPC Device Protection” on page 16. DCLK DATA0 nSTATUS CONF_DONE nCONFIG VCC GND (3) nCE (3) FPGA0 VCC DCLK DATA0 nCONFIG nCE DCLK DATA0 GND GND FPGA1 FPGA7 EPC Device DCLK DATA0 OE nCS nINIT_CONF (2) WE#C RP#C WE#F RP#F A[20..0] RY/BY# CE# OE# DQ[15..0] DATA1 nSTATUS CONF_DONE nSTATUS CONF_DONE nCONFIG nCE DATA 7 N.C. N.C. N.C. N.C. N.C. (3) (3) EXCLK PORSEL PGM[2..0] GND TMO WP# VCC VCCW BYTE# (5) TM1 C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) A0-F A1-F A15-F A16-F MSEL MSEL MSEL n n n (6) (6) (6) (1) (1) nCEO N.C. nCEO N.C. nCEO N.C. (1) (4) (4) (4) VCC (7) |
类似零件编号 - EP2SGX60D |
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类似说明 - EP2SGX60D |
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