数据搜索系统,热门电子元器件搜索 |
|
EP2SGX90F 数据表(PDF) 95 Page - Altera Corporation |
|
EP2SGX90F 数据表(HTML) 95 Page - Altera Corporation |
95 / 316 page Altera Corporation 2–87 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Figure 2–60. DSP Block Interface to Interconnect A bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2–23. f Refer to the DSP Blocks in Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information on DSP blocks. LAB LAB Row Interface Block DSP Block Row Structure 16 OA[17..0] OB[17..0] A[17..0] B[17..0] DSP Block to LAB Row Interface Block Interconnect Region 36 Inputs per Row 36 Outputs per Row R4 Interconnect C4 Interconnect Direct Link Interconnect from Adjacent LAB Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB 36 36 36 36 Control 12 16 18 |
类似零件编号 - EP2SGX90F |
|
类似说明 - EP2SGX90F |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |