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EP2SGX90F 数据表(PDF) 95 Page - Altera Corporation

部件名 EP2SGX90F
功能描述  Section I. Stratix II GX Device Data Sheet
Download  316 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2SGX90F 数据表(HTML) 95 Page - Altera Corporation

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Altera Corporation
2–87
October 2007
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Figure 2–60. DSP Block Interface to Interconnect
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in Table 2–23.
f
Refer to the DSP Blocks in Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook for more information on DSP blocks.
LAB
LAB
Row Interface
Block
DSP Block
Row Structure
16
OA[17..0]
OB[17..0]
A[17..0]
B[17..0]
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
R4 Interconnect
C4 Interconnect
Direct Link Interconnect
from Adjacent LAB
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
36
36
36
36
Control
12
16
18


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