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EP2SGX60D 数据表(PDF) 11 Page - Altera Corporation

部件名 EP2SGX60D
功能描述  Section I. Stratix II GX Device Data Sheet
Download  316 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2SGX60D 数据表(HTML) 11 Page - Altera Corporation

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Altera Corporation
2–3
October 2007
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Figure 2–2. Elements of the Transceiver Block
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
The receiver contains the following:
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Byte ordering
Receiver phase compensation FIFO buffer
Designers can preset Stratix II GX transceiver functions using the
Quartus® II software. In addition, pre-emphasis, equalization, and
differential output voltage (VOD) are dynamically programmable. Each
Stratix II GX transceiver channel supports various loopback modes and is
Channel 1
Channel 0
Channel 2
Supporting Blocks
(PLLs, State Machines,
Programming)
Channel 3
RX1
TX1
RX0
TX0
RX2
TX2
RX3
TX3
REFCLK_1
REFCLK_0
Transceiver Block
Stratix II GX
Logic Array


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