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EP2SGX60D 数据表(PDF) 82 Page - Altera Corporation |
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EP2SGX60D 数据表(HTML) 82 Page - Altera Corporation |
82 / 316 page 2–74 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 TriMatrix Memory Figure 2–51. M4K RAM Block Control Signals The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–52 shows the M4K RAM block to logic array interface. clock_b clocken_a clock_a clocken_b aclr_b aclr_a Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect renwe_b renwe_a 6 |
类似零件编号 - EP2SGX60D |
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类似说明 - EP2SGX60D |
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