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EP2SGX60D 数据表(PDF) 86 Page - Altera Corporation |
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EP2SGX60D 数据表(HTML) 86 Page - Altera Corporation |
86 / 316 page 2–78 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 TriMatrix Memory Figure 2–55. M-RAM Block LAB Row Interface Note (1) Note to Figure 2–55: (1) Only R24 and C16 interconnects cross the M-RAM block boundaries. M-RAM Block Port B Port A Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block Row Unit Interface Allows LAB Rows to Drive Port A Datain, Dataout, Address and Control Signals to and from M-RAM Block LABs in Row M-RAM Boundary LABs in Row M-RAM Boundary LAB Interface Blocks L0 L1 L2 L3 L4 L5 R0 R1 R2 R3 R4 R5 |
类似零件编号 - EP2SGX60D |
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类似说明 - EP2SGX60D |
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