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EP2SGX30D 数据表(PDF) 63 Page - Altera Corporation |
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EP2SGX30D 数据表(HTML) 63 Page - Altera Corporation |
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63 / 316 page  Altera Corporation 2–55 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Figure 2–40. Template for Supported Seven-Input Functions in Extended LUT Mode Note to Figure 2–40: (1) If the seven-input function is un-registered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arithmetic Mode The arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of two four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in Figure 2–41, the carry-in signal feeds to adder0 , and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or un-registered versions of the adder outputs. datae0 combout0 5-Input LUT 5-Input LUT datac dataa datab datad dataf0 datae1 dataf1 DQ To general or local routing To general or local routing reg0 This input is available for register packing. (1) |
类似零件编号 - EP2SGX30D |
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类似说明 - EP2SGX30D |
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