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EP2SGX30D 数据表(PDF) 47 Page - Altera Corporation |
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EP2SGX30D 数据表(HTML) 47 Page - Altera Corporation |
47 / 316 page Altera Corporation 2–39 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Table 2–11 summarizes the possible clocking connections for the transceivers. Clock Resource for PLD-Transceiver Interface For the regional or global clock network to route into the transceiver, a local route input output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for connecting with LRIO clocks. These resources are limited and determine the number of clocks that can be used between the PLD and transceiver blocks. Table 2–12 shows the number of LRIO resources available for Stratix II GX devices with different numbers of transceiver blocks. Tables 2–12 through 2–15 show the connection of the LRIO clock resource to the transceiver block. Table 2–11. Available Clocking Connections for Transceivers Source Destination Transmitter PLL Receiver PLL Global Clock Regional Clock Inter-Transceiver Lines REFCLK[1..0] vv v v v Transmitter PLL vv Receiver PLL vv Global clock (driven from an input pin) vv Inter-transceiver lines vv Table 2–12. Available Clocking Connections for Transceivers in 2SGX30D Region Clock Resource Transceiver Global Clock Regional Clock Bank 13 8 Clock I/O Bank 14 8 Clock I/O Region0 8 LRIO clock v RCLK 20-27 v Region1 8 LRIO clock v RCLK 12-19 v |
类似零件编号 - EP2SGX30D |
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类似说明 - EP2SGX30D |
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