LA72715NV

No.A1770-9/13

Continued from preceding page.

Pin

No.

Pin Name

DC voltage

AC level

Function

Equivalent Circuit

16

SLAVE ADD

SELECT

17

18

Line Out (R)

terminal

Line Out (L)

terminal

DC : 2.4V

AC : -4.5dBV

Line output pin.

250

Ω 300Ω

50k

Ω

50k

Ω

2.5pF

2.5pF

PAD

19

VCC5V

20

MTS MODE

OUT

No signal

DC : 2.0V

Detection output for M.T.S. signal.

BILINGUAL

:3.0V

MONO

:2.0V

STEREO

:1.0V

10k

Ω

10k

Ω

PAD

21

REG FILT

DC : 2.4V

Filter terminal of reference voltage source

10k

Ω

10k

Ω

10k

Ω

500

Ω

50k

Ω

500

Ω

PAD

22

23

24

NC

I

(1) Data Transfer Manual

data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale

of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI

stop condition, thus the transfer comes to close.

*1 Defined by SCL rise down SDA during ‘H’ period.

*2 Defined by SCL rise up SDA during ‘H’ period.

(2) Transfer Data Format

After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition

(See figure 1).

this LSI side, this is input operation mode), and in case of ‘H’ reading mode (As this LSI side, this is output

operation mode).

Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be

canceled the transfer dates. At READ mode, this LSI outputs during ACK period, please must input 9 clocks.

*3 It is called R/W bit.