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ADSP-21160NCBZ-100 数据表(PDF) 8 Page - Analog Devices |
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ADSP-21160NCBZ-100 数据表(HTML) 8 Page - Analog Devices |
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8 / 60 page  Rev. C | Page 8 of 60 | February 2013 ADSP-21160M/ADSP-21160N interrupt generation upon completion of DMA transfers, two- dimensional DMA, and DMA chaining for automatic linked DMA transfers. Multiprocessing The ADSP-21160x offers powerful features tailored to multipro- cessing DSP systems as shown in M. The external port and link ports provide integrated glueless multiprocessing support. The external port supports a unified address space (see Figure 4) that allows direct interprocessor accesses of each processor’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21160x processors and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for sema- phores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 400M bytes/s (ADSP-21160N) over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21160x DSPs and can be used to implement reflective semaphores. Six link ports provide for a second method of multiprocessing communications. Each link port can support communications to another ADSP-21160x. Using the links, a large multiproces- sor system can be constructed in a 2D or 3D fashion. Systems can use the link ports and cluster multiprocessing concurrently or independently. Link Ports The processor features six 8-bit link ports that provide addi- tional I/O capabilities. With the capability of running at 100 MHz rates, each link port can support 100M bytes/s (ADSP-21160N). Link port I/O is especially useful for point-to- point interprocessor communication in multiprocessing sys- tems. The link ports can operate independently and simultaneously. Link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or DMA- transferred to on-chip memory. Each link port has its own dou- ble-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are pro- grammable as transmit or receive. Serial Ports The processor features two synchronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate up to half the clock rate of the core, providing each with a maxi- mum data rate of 50M bits/s (ADSP-21160N). Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports offers a TDM multichannel mode. The serial ports can operate with little-endian or big-endian trans- mission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding. Serial port clocks and frame syncs can be generated internally or externally. Host Processor Interface The ADSP-21160x host interface allows easy connection to standard microprocessor buses, both 16- and 32-bit, with little additional hardware required. The host interface is accessed through the ADSP-21160x DSP’s external port and is memory- mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor communicates with the ADSP-21160x DSP’s external bus with host bus request (HBR), host bus grant (HBG), ready (REDY), acknowledge (ACK), and chip select (CS) signals. The host can directly read and write the internal memory of the processor, and can access the DMA channel setup and mailbox registers. Vector interrupt support provides efficient execution of host commands. The host processor interface can be used in either multiproces- sor or uniprocessor systems. For multiprocessor systems, host access to the SHARC requires that address pins ADDR17, ADDR18, ADDR19, and ADDR20 be driven low. It is not enough to tie these pins to ground through a resistor (for exam- ple, 10 k). These pins must be driven low with a strong enough drive strength (10 to 50 ) to overcome the SHARC keeper latches present on these pins. If the drive strength provided is not strong enough, data access failures can occur. For uniprocessor SHARC systems using this host access feature, address pins ADDR17, ADDR18, ADDR19, and ADDR20 may be tied low (for example, through a 10 k ohm resistor), driven low by a buffer/driver, or left floating. Any of these options is sufficient. Figure 5. External Data Alignment Options DATA63–0 63 55 47 39 3123 15 7 0 RDH/WRH RDL/WRL EPROM 16-BIT PACKED 32-BIT PACKED 64-BIT TRANS. FOR 40-BIT EXT. PRECISION 64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS: 64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS BYTE 0 BYTE 7 32-BIT NORMAL WD. (EVEN ADDR.) 32-BIT NORMAL WORD (ODD ADDR) |
类似零件编号 - ADSP-21160NCBZ-100 |
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类似说明 - ADSP-21160NCBZ-100 |
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