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MPC8347ECZUAJFB 数据表(PDF) 27 Page - Freescale Semiconductor, Inc |
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MPC8347ECZUAJFB 数据表(HTML) 27 Page - Freescale Semiconductor, Inc |
27 / 99 page MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 27 Ethernet: Three-Speed Ethernet, MII Management Figure 11 shows the MII transmit AC timing diagram. Figure 11. MII Transmit AC Timing Diagram 8.2.2.2 MII Receive AC Timing Specifications Table 28 provides the MII receive AC timing specifications. TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 28. MII Receive AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition Symbol1 Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX — 400 — ns RX_CLK clock period 100 Mbps tMRX —40— ns RX_CLK duty cycle tMRXH/tMRX 35 — 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns Table 27. MII Transmit AC Timing Specifications (continued) At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition Symbol1 Min Typ Max Unit TX_CLK TXD[3:0] tMTKHDX tMTX tMTXH tMTXR tMTXF TX_EN TX_ER |
类似零件编号 - MPC8347ECZUAJFB |
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类似说明 - MPC8347ECZUAJFB |
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