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ST16C654IJ68 数据表(PDF) 9 Page - Exar Corporation |
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ST16C654IJ68 数据表(HTML) 9 Page - Exar Corporation |
9 / 51 page xr ST16C654/654D REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 9 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 654 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS VCC VCC DSRA# CTSA# RTSA# DTRA# RXA TXA RIA# CDA# GND A0 A1 A2 UART_CSA# UART_CSB# IOR# IOW# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CSA# CSB# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART Channel A UART Channel B UART_INTB UART_INTA INTB INTA UART_RESET RESET Serial Interface of RS-232 Serial Interface of RS-232 Intel Data Bus (16 Mode) Interconnections UART Channel C UART Channel D Similar to Ch A Similar to Ch A Similar to Ch A UART_INTD UART_INTC INTD INTC UART_CSC# UART_CSD# CSC# CSD# VCC 16/68# VCC VCC GND A0 A1 A2 UART_CS# A3 R/W# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CSA# CSB# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART_IRQ# INTB INTA RESET# Serial Interface of RS-232 Serial Interface of RS-232 Motorola Data Bus (68 Mode) Interconnections VCC UART_RESET# (no connect) DSRA# CTSA# RTSA# DTRA# RXA TXA RIA# CDA# UART Channel A UART Channel B UART Channel C Similar to Ch A Similar to Ch A Similar to Ch A INTC (no connect) INTD (no connect) A4 CSC# CSD# VCC 16/68# UART Channel D |
类似零件编号 - ST16C654IJ68 |
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类似说明 - ST16C654IJ68 |
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