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74LVC2G00DC-G 数据表(PDF) 8 Page - NXP Semiconductors

部件名 74LVC2G00DC-G
功能描述  Dual 2-input NAND gate
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

74LVC2G00DC-G 数据表(HTML) 8 Page - NXP Semiconductors

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74LVC2G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 8 April 2013
8 of 20
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5
 V
CC
0.5
 V
CC
2.3 V to 2.7 V
0.5
 V
CC
0.5
 V
CC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5
 V
CC
0.5
 V
CC
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 9.
Test circuit for measuring switching times
VEXT
VCC
VI
VO
001aae235
DUT
CL
RT
RL
RL
PULSE
GENERATOR
VM
VM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VM
VM
90 %
10 %
tf
tr
tr
tf
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
 2.0 ns
30 pF
1 k
open
2.3 V to 2.7 V
VCC
 2.0 ns
30 pF
500
open
2.7 V
2.7 V
 2.5 ns
50 pF
500
open
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500
open
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
500
open


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