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L9D232M64SBG5 数据表(PDF) 100 Page - LOGIC Devices Incorporated |
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L9D232M64SBG5 数据表(HTML) 100 Page - LOGIC Devices Incorporated |
100 / 115 page CK CK# Command Don’t Care T0 T1 Valid PRE T2 NOP T3 t CKE (MIN) CKE Power-down 1 entry 1 x tCK Address A10 Valid All banks vs Single bank Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × t CK after the PRECHARGE command. Precharge power-down entry occurs prior to t RP (MIN) being satisfied. LOGIC Devices Incorporated www.logicdevices.com September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E 100 2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD) L9D232M64SBG5 L9D232M72SBG5 L9D232M80SBG5 L9D264M64SBG5 L9D264M72SBG5 L9D264M80SBG5 High Performance, Integrated Memory Module Product FIGURE 69 - PRECHARGE COMMAND-TO-POWER-DOWN ENTRY |
类似零件编号 - L9D232M64SBG5 |
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类似说明 - L9D232M64SBG5 |
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