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MT47H256M8 数据表(PDF) 90 Page - Micron Technology

部件名 MT47H256M8
功能描述  2Gb: x4, x8, x16 DDR2 SDRAM Features
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT47H256M8 数据表(HTML) 90 Page - Micron Technology

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10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
(that is, to program operating parameters without resetting the DLL). To access the MR,
set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register
(MR) (page 77) for all MR requirements.
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,
and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0
HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 82) for all EMR require-
ments.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and
E9 to “0,” and then setting all other desired parameters. To access the extended mode
registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-
ter the DLL RESET at Tf0.
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-
tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the ap-
propriate configuration (x4, x8, x16); DQ represents DQ[3:0] for x4, DQ[7:0] for x8 and
DQ[15:0] for x16.
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
required to be decoded).
2Gb: x4, x8, x16 DDR2 SDRAM
Initialization
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
90
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.


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