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MT47H256M8 数据表(PDF) 82 Page - Micron Technology |
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MT47H256M8 数据表(HTML) 82 Page - Micron Technology |
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82 / 134 page  Extended Mode Register (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on- die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func- tions are controlled via the bits shown in Figure 38. The EMR is programmed via the LM command and will retain the stored information until it is programmed again or the de- vice loses power. Reprogramming the EMR will not alter the contents of the memory ar- ray, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent opera- tion. Violating either of these requirements could result in an unspecified operation. Figure 38: EMR Definition DLL Posted CAS# R TT Out A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended mode register (Ex) Address bus 97 6 5 4 3 82 1 0 A10 A12 BA0 BA1 10 11 12 n 0 14 E1 0 1 Output Drive Strength Full Reduced Posted CAS# Additive Latency (AL) 3 0 1 2 3 4 5 6 Reserved E3 0 1 0 1 0 1 0 1 E4 0 0 1 1 0 0 1 1 E5 0 0 0 0 1 1 1 1 0 1 DLL Enable Enable (normal) Disable (test/debug) E0 15 E11 0 1 RDQS Enable No Yes OCD Program An 2 ODS R TT DQS# E10 0 1 DQS# Enable Enable Disable RDQS R TT (Nominal) R TT disabled 75 150 50 E2 0 1 0 1 E6 0 0 1 1 0 1 Outputs Enabled Disabled E12 0 1 0 1 Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) E15 0 0 1 1 E14 MRS BA2 1 16 0 OCD Operation 4 OCD exit Reserved Reserved Reserved Enable OCD defaults E7 0 1 0 0 1 E8 0 0 1 0 1 E9 0 0 0 1 1 Notes: 1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be pro- grammed to “0.” 2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re- served for future use and must be programmed to “0.” 3. Not all listed AL options are supported in any individual speed grade. 4. As detailed in the Initialization (page 88) section notes, during initialization of the OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before initialization is finished. 2Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) PDF: 09005aef824f87b6 2Gb_DDR2.pdf – Rev. H 10/11 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. |
类似零件编号 - MT47H256M8 |
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类似说明 - MT47H256M8 |
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