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AM53CF96JCW 数据表(PDF) 2 Page - Advanced Micro Devices |
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AM53CF96JCW 数据表(HTML) 2 Page - Advanced Micro Devices |
2 / 76 page P R E L I M I N A R Y AMD 2 Am53CF94/Am53CF96 parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD’s exclusive power-down feature can be enabled to help reduce power consumption during the chip’s sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers. The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD’s GLITCH EATER Circuitry therefore maintains system perform- ance and improves reliability. The following diagram illustrates this circuit’s operation. The Am53CF94 is also available in a 3.3 V version. SCSI Environment Device without the GLITCH EATER Circuit AMD’s Device with the GLITCH EATER Circuit GLITCH EATER Circuitry in SCSI Environment Note: The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default setting is 12 ns (single-ended). 17348B-1 Glitch Window SYSTEM BLOCK DIAGRAM 9 CPU DMA Memory Am53CF94/96 8 16 16 4 9 SCSI Data 16 DMA Addr Data SCSI Control 16 17348B-2 |
类似零件编号 - AM53CF96JCW |
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类似说明 - AM53CF96JCW |
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