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ADSP-21160MKB-80 数据表(PDF) 1 Page - Analog Devices |
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ADSP-21160MKB-80 数据表(HTML) 1 Page - Analog Devices |
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1 / 60 page  SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com SUMMARY High performance 32-bit DSP—applications in audio, medi- cal, military, graphics, imaging, and communication Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-over- head I/O Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing fea- tures, and ports (serial, link, external bus, and JTAG) FEATURES 100 MHz (10 ns) core instruction rate (ADSP-21160N) Single-cycle instruction execution, including SIMD opera- tions in both computational units Dual data address generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping and single-cycle loop setup, provid- ing efficient program sequencing IEEE 1149.1 JTAG standard Test Access Port and on-chip emulation 400-ball 27 mm × 27 mm PBGA package Available in lead-free (RoHS compliant) package 200 million fixed-point MACs sustained performance (ADSP-21160N) Figure 1. Functional Block Diagram MULT ALU BARREL SHIFTER DATA REGISTER FILE (PEY) 16 x 40-BIT MULT ALU BARREL SHIFTER DATA REGISTER FILE (PEX) 16x40-BIT SERIAL PORTS (2) LINK PORTS (6) 4 6 6 60 IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS AND DATA BUFFERS I/O PROCESSOR DMA CONTROLLER TIMER INSTRUCTION CACHE 32x48-BIT ADDR DATA DATA DATA ADDR ADDR DATA ADDR TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT I/O PORT DUAL-PORTED SRAM JTAG TEST AND EMULATION 6 HOST PORT ADDR BUS MUX IOA 18 IOD 64 MULTIPROCESSOR INTERFACE EXTERNAL PORT DATA BUS MUX 64 32 32 PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS DM DATA BUS BUS CONNECT (PX) DAG1 8x4 x 32 32 16/32/40/48/64 32/40/64 CORE PROCESSOR PROGRAM SEQUENCER DAG2 8x 4x 32 |
类似零件编号 - ADSP-21160MKB-80 |
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类似说明 - ADSP-21160MKB-80 |
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