AD9516-5PCBZ datasheet(9/76 Pages) AD

部件名	AD9516-5PCBZ

功能描述	14-Output Clock Generator

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制造商	AD [Analog Devices]

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AD9516-5

Rev. A | Page 9 of 76

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

fs rms

Calculated from SNR of ADC method

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

285

fs rms

Calculated from SNR of ADC method

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

350

fs rms

Calculated from SNR of ADC method

DELAY BLOCK ADDITIVE TIME JITTER

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1

Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adjust 000000b

0.54

ps rms

Delay (1600 μA, 0x1C) Fine Adjust 101111b

0.60

ps rms

Delay (800 μA, 0x1C) Fine Adjust 000000b

0.65

ps rms

Delay (800 μA, 0x1C) Fine Adjust 101111b

0.85

ps rms

Delay (800 μA, 0x4C) Fine Adjust 000000b

0.79

ps rms

Delay (800 μA, 0x4C) Fine Adjust 101111b

1.2

ps rms

Delay (400 μA, 0x4C) Fine Adjust 000000b

1.2

ps rms

Delay (400 μA, 0x4C) Fine Adjust 101111b

2.0

ps rms

Delay (200 μA, 0x1C) Fine Adjust 000000b

1.3

ps rms

Delay (200 μA, 0x1C) Fine Adjust 101111b

2.5

ps rms

Delay (200 μA, 0x4C) Fine Adjust 000000b

1.9

ps rms

Delay (200 μA, 0x4C) Fine Adjust 101111b

3.8

ps rms

1 This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

类似零件编号 - AD9516-5PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	AD9516-5PCBZ	1Mb / 76P	14-Output Clock Generator REV. A

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类似说明 - AD9516-5PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	AD9516-5BCPZ	1Mb / 76P	14-Output Clock Generator REV. A
	AD9516-4	1Mb / 84P	14-Output Clock Generator with Integrated 1.6 GHz VCO REV. 0
	AD9516-3	957Kb / 84P	14-Output Clock Generator with Integrated 2.0 GHz VCO REV. 0
	AD9516-2	946Kb / 84P	14-Output Clock Generator with Integrated 2.2 GHz VCO REV. 0
	AD9516-2	1Mb / 80P	14-Output Clock Generator with Integrated 2.2 GHz VCO REV. C
	AD9516-3	1Mb / 80P	14-Output Clock Generator with Integrated 2.0 GHz VCO REV. C
	AD9516-4	1Mb / 80P	14-Output Clock Generator with Integrated 1.6 GHz VCO REV. C
	AD9516-1	1Mb / 84P	14-Output Clock Generator with Integrated 2.5 GHz VCO REV. 0
	AD9518-3	1,002Kb / 64P	6-Output Clock Generator with 6-Output Clock Generator with REV. B
	AD9516-0	1Mb / 84P	14-Output Clock Generator with Integrated 2.8 GHz VCO REV. 0

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