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AD8842ANZ 数据表(PDF) 11 Page - Analog Devices |
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AD8842ANZ 数据表(HTML) 11 Page - Analog Devices |
11 / 13 page AD8842 REV. –11– Figure 32 shows a three-wire interface for a single AD8842 that easily cascades for multiple packages. This circuit topology often called daisy chaining requires preformating all the serial data for each package in the chain. In the case of the 3 packages shown a 36 bit data word must be completely clocked into all the AD8842 serial data input registers then the LD strobe would transfer the data bits into the DAC registers updating one DAC in each package. Figure 32. Three-Wire Interface Updates Multiple AD8842s Figure 31. Addressing Multiple AD8842 Packages There is some digital feedthrough from the digital input pins. Operating the clock only when the DAC registers require updat- ing minimizes the effect of the digital feedthrough on the analog signal channels. Measurements of DAC switch feedthrough shown in the electrical characteristics table were accomplished by grounding the VINx inputs and cycling the data codes be- tween all zeros and all ones. Under this condition 5 nV-s of feedthrough was measured on the output of the switched DAC channel. An adjacent channel measured less than 1 nV-s of digi- tal crosstalk. The digital feedthrough and crosstalk photographs shown in the typical performance characteristics section display these characteristics (Figures 15 and 17). AD8842 #2 LD CLK SDI AD8842 #1 LD CLK SDI AD8842 #N LD CLK SDI • • • CLOCK DATA CODED PACKAGE ADDRESS WR ADDRESSS DECODE EN • • • ANALOG CONNECTIONS OMITTED FOR CLARITY µC PA0 PA1 PA2 DATA CLOCK LD DAC A SDI CLK AD8842 #1 LD SDO DAC H DAC A SDI CLK AD8842 #2 LD SDO DAC H DAC A SDI CLK AD8842 #3 LD SDO DAC H • • VOU VO • • • A |
类似零件编号 - AD8842ANZ |
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类似说明 - AD8842ANZ |
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