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TLA7SA00 数据表(PDF) 7 Page - List of Unclassifed Manufacturers |
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TLA7SA00 数据表(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 14 page Acquisition system (with P67SA00 series probes) Dynamic link width switch latency Consumes up to 48 symbols (typical) Dynamic link rate switch latency <200 ns EIDLE time (typical) (with either internal reference clock or spread spectrum using external reference clock) Maximum time to change to Gen1 rate 2 TS1 Maximum time to change to Gen2 rate 1 EIEOS + 3 TS1 Maximum time to change to Gen3 rate 1 EIEOS + 6 TS1 Number of FTS packets required to resync following L0s exit Assumes an EIDLE ranging from 20 ns to 2 ms, with either internal reference clock or spread spectrum using external reference clock Gen1 4 FTS (typical) Gen2 1 EIEOS + 6 FTS (typical) Gen3 1 EIEOS + 4 FTS (typical) Filter specifications Ordered sets TS1, TS2, SKP, EIOS, FTS, EIEOS, SDS DLLPs Ack, Nak, PM, Vendor specific, FC1, FC2, UpdateFC TLPs MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk, FetchAdd, Swap, CAS, LPrfx, EPrfx Trigger system Independent Trigger states 8 Trigger sequence rate Operates at symbol rate time (Gen1, Gen2, Gen3) Maximum independent If/Then clauses per state 8 Maximum number of events per If/ Then clause 8 Maximum number of actions per If/ Then clause 8 Maximum number of event counters per state 2 Event counter range 31 bit Number of TLP packet recognizers per link direction 4 Number of DLLP packet recognizers per link direction 4 Number of sequence recognizers 4 TLA7SA00 Logic Protocol Analyzer Datasheet www.tektronix.com 7 |
类似零件编号 - TLA7SA00 |
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类似说明 - TLA7SA00 |
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