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EP1K50 数据表(PDF) 51 Page - Altera Corporation

部件名 EP1K50
功能描述  Programmable Logic Device Family
Download  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1K50 数据表(HTML) 51 Page - Altera Corporation

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Altera Corporation
51
ACEX 1K Programmable Logic Device Family Data Sheet
13
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the ACEX 1K device.
Figure 24. ACEX 1K Device Timing Model
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Figure 25. ACEX 1K Device LE Timing Model
Dedicated
Clock/Input
Interconnect
I/O Element
Logic
Element
Embedded Array
Block
tCGENR
tCO
tCOMB
tSU
tH
tPRE
tCLR
Register
Delays
LUT Delay
tLUT
tRLUT
tCLUT
Carry Chain
Delay
Carry-In
Cascade-In
Data-Out
tCGEN
tCICO
Packed Register
Delay
tPACKED
Register Control
Delay
tC
tEN
Data-In
Control-In
tCASC
Cascade-Out
Carry-Out
tLABCARRY
tLABCASC


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