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EP1K10 数据表(PDF) 83 Page - Altera Corporation

部件名 EP1K10
功能描述  Programmable Logic Device Family
Download  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1K10 数据表(HTML) 83 Page - Altera Corporation

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Altera Corporation
83
ACEX 1K Programmable Logic Device Family Data Sheet
13
Figure 31. ACEX 1K ICCACTIVE vs. Operating Frequency
Configuration &
Operation
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50
µs.
1
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
0
Frequency (MHz)
300
200
100
50
100
EP1K100
ICC Supply
Current (mA)
0
Frequency (MHz)
ICC Supply
Current (mA)
100
80
60
40
20
50
100
EP1K30
0
Frequency (MHz)
ICC Supply
Current (mA)
200
150
100
50
50
100
EP1K50


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