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AD7303BN 数据表(PDF) 3 Page - Analog Devices |
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AD7303BN 数据表(HTML) 3 Page - Analog Devices |
3 / 16 page AD7303 –3– REV. 0 TIMING CHARACTERISTICS1, 2 Parameter Limit at TMIN, TMAX (B Version) Units Conditions/Comments t1 33 ns min SCLK Cycle Time t2 13 ns min SCLK High Time t3 13 ns min SCLK Low Time t4 5 ns min SYNC Setup Time t5 5 ns min Data Setup Time t6 4.5 ns min Data Hold Time t7 4.5 ns min SYNC Hold Time t8 33 ns min Minimum SYNC High Time NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2, tr and tf should not exceed 1 µs on any input. 2See Figures 1 and 2. SCLK (I) SYNC (I) DIN (I) DB15 DB0 t5 t6 t2 t3 t4 t7 t4 t8 t1 Figure 1. Timing Diagram for Continuous 16-Bit Write SCLK (I) SYNC (I) DIN (I) DB15 DB8 t5 t6 t2 t3 t4 t7 DB7 DB0 t5 t6 t8 t1 Figure 2. Timing Diagram for 2 × 8-Bit Writes (VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference; all specifications TMIN to TMAX unless otherwise noted) |
类似零件编号 - AD7303BN |
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类似说明 - AD7303BN |
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