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LM2512A 数据表(PDF) 10 Page - Texas Instruments |
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LM2512A 数据表(HTML) 10 Page - Texas Instruments |
10 / 28 page Bus Phase MC MDn Active Power-Off 1 H = ( 1*I) L = (5*I) O = (0*I) H = ( 1*I) L = (5*I) O = (0*I) Current Waveforms MC-out (SER)/ MC-in (DES) Link-Up Link Off Bus Phase PD* (SER) active PCLK (SER) MDn-out (SER)/MDn-in (DES) PD* (DES) PCLK remains ON t0 t1 t2 t3 t4 LM2512A SNLS269B – AUGUST 2007 – REVISED MAY 2013 www.ti.com Figure 9. MPL Power Up Timing OFF PHASE In the OFF phase, MPL transmitters are turned off with zero current flowing on the MC and MDn lines. Figure 10 shows the transition of the MPL bus into the OFF phase. If an MPL line is driven to a logical Low (high current) when the OFF phase is entered it may temporarily pass through as a logical High (low current) before reaching the zero line current state. The link may be powered down by asserting both the SER’s and DES’s PD* input pins (Low) or by stopping the PCLK (DES dependant). This causes the devices to immediately put the link to the OFF Phase and internally enter a low power state. Figure 10. Bus Power Down Timing RGB VIDEO INTERFACE The LM2512A is transparent to data format and control signal timing. Each PCLK, RGB inputs, HS, VS and DE are sampled on the rising edge of the PCLK. A PCLK by PCLK representation of these signals is duplicated on the opposite device after being transferred across the MPL Level-0 interface. The LM2512A can accommodate a wide range of display formats. QVGA to VGA can be supported within the 2MHz to 20 MHz PCLK input range. The 24-bit RGB (R0-7, G0-7, B0-7) color information is dithered to 18 bits then serialized, followed by the control bits VS (VSYNC), HS (HSYNC), DE (Data Enable) and PE (Odd Parity) and Frame Sequence (F[1:0]) bits. The default configuration is for 2 MD lanes plus the MC. Via the SPI Interface, the Serializer can be configured for a 3 MD Lane configuration. When transporting color depth below 24-bit, the 24-bit protocol can be used by offsetting the color data. The LSBs of the RGB are not used and data is offset toward the upper (MSB) end of the bit fields. Unused inputs should be tied off. At a maximum PCLK of 20 MHz (3MDs), a 80MHz MC clock is generated. The data lane rate uses both clock edges, thus 160Mbps (raw) are sent per MD lane. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM2512A |
类似零件编号 - LM2512A |
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类似说明 - LM2512A |
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