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JS28F320J3F75A 数据表(PDF) 24 Page - Numonyx B.V

部件名 JS28F320J3F75A
功能描述  Numonyx짰 Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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制造商  NUMONYX [Numonyx B.V]
网页  http://www.numonyx.com
标志 NUMONYX - Numonyx B.V

JS28F320J3F75A 数据表(HTML) 24 Page - Numonyx B.V

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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
Jan 2011
24
208032-03
7.1
Read Specifications
Notes:
1.
CEX low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see
Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2.
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX (see note 1 and Table 17, “Chip Enable Truth
Table for 32-, 64-, 128-Mb” on page 30) without impact on tELQV.
4.
See
Figure 13, “AC Input/Output Reference Waveform” on page 29 and Figure 14, “Transient
Equivalent Testing Load Circuit” on page 29 for testing characteristics.
5.
Sampled, not 100% tested.
6.
For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Table 11: Read Operations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Density
Min
Max
Unit
Notes
R1
tAVAV
Read/Write Cycle Time
All
75
ns
1,2
R2
tAVQV
Address to Output Delay
75
ns
1,2
R3
tELQV
CEX to Output Delay
75
ns
1,2
R4
tGLQV
OE# to Non-Array Output Delay
25
ns
1,2,4
R5
tPHQV
RP# High to Output Delay
32 Mbit
150
ns
1,2
64 Mbit
180
1,2
128 Mbit
210
1,2
R6
tELQX
CEX to Output in Low Z
All
0
ns
1,2,5
R7
tGLQX
OE# to Output in Low Z
0
ns
1,2,5
R8
tEHQZ
CEX High to Output in High Z
25
ns
1,2,5
R9
tGHQZ
OE# High to Output in High Z
15
ns
1,2,5
R10
tOH
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
0
ns
1,2,5
R11
tELFL/tELFH
CEX Low to BYTE# High or Low
10
ns
1,2,5
R12
tFLQV/tFHQV
BYTE# to Output Delay
1
µs
1,2
R13
tFLQZ
BYTE# to Output in High Z
1
µs
1,2,5
R14
tEHEL
CEx High to CEx Low
0
ns
1,2,5
R15
tAPA
Page Address Access Time
25
ns
5, 6
R16
tGLQV
OE# to Array Output Delay
25
ns
1,2,4


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