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CAT24M01YE-GT3 数据表(PDF) 3 Page - ON Semiconductor |
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CAT24M01YE-GT3 数据表(HTML) 3 Page - ON Semiconductor |
3 / 14 page CAT24M01 http://onsemi.com 3 Table 4. PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified. Symbol Parameter Conditions Max Units CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF IWP, IA (Note 6) WP Input Current, Address Input Current (A1, A2) VIN < VIH, VCC = 5.5 V 75 mA VIN < VIH, VCC = 3.3 V 50 VIN < VIH, VCC = 1.8 V 25 VIN > VIH 2 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 6. When not driven, the WP, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 5. A.C. CHARACTERISTICS (Note 7) VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified. Symbol Parameter Standard VCC = 1.8 V − 5.5 V Fast VCC = 1.8 V − 5.5 V Fast−Plus VCC = 2.5 V − 5.5 V TA = −405C to +855C Units Min Max Min Max Min Max FSCL Clock Frequency 100 400 1,000 kHz tHD:STA START Condition Hold Time 4 0.6 0.25 ms tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms tHIGH High Period of SCL Clock 4 0.6 0.40 ms tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 8) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 8) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms tBUF Bus Free Time Between STOP and START 4.7 1.3 0.5 ms tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms tDH Data Out Hold Time 50 50 50 ns Ti (Note 8) Noise Pulse Filtered at SCL and SDA Inputs 50 50 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR Write Cycle Time 5 5 5 ms tPU (Notes 8, 9) Power-up to Ready Mode 0.1 0.1 0.1 ms 7. Test conditions according to “A.C. Test Conditions” table. 8. Tested initially and after a design or process change that affects this parameter. 9. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF |
类似零件编号 - CAT24M01YE-GT3 |
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类似说明 - CAT24M01YE-GT3 |
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