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CAT24C21LE 数据表(PDF) 3 Page - ON Semiconductor

部件名 CAT24C21LE
功能描述  1 kb Dual Mode Serial EEPROM for VESA Plug-and-Play
Download  14 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

CAT24C21LE 数据表(HTML) 3 Page - ON Semiconductor

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CAT24C21
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Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.)
Symbol
Parameter
Min
Max
Units
TRANSMIT−ONLY MODE
TVAA
Output valid from VCLK
0.5
ms
TVHIGH
VCLK high
0.6
ms
TVLOW
VCLK low
1.3
ms
TVHZ
Mode transition
0.5
ms
TVPU
Transmit−only power−up
0
ns
READ & WRITE CYCLE LIMITS
FSCL
Clock Frequency
400
kHz
TI (Note 8)
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
tAA
SCL Low to SDA Data Out and ACK Out
1
ms
tBUF (Note 8)
Time the Bus Must be Free Before a New Transmission Can Start
1.2
ms
tHD:STA
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time
0.6
ms
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
50
ns
tR (Note 8)
SDA and SCL Rise Time
0.3
ms
tF (Note 8)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
ms
tDH
Data Out Hold Time
100
ns
POWER−UP TIMING (Note 8 and 9)
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
WRITE CYCLE LIMITS
tWR
Write Cycle Time
5
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are
disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
Pin Description
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the bi−directional
mode.
The SDA bi−directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire−ORed with other open
drain or open collector outputs.
Functional Description
The CAT24C21 has two modes of operation: the
transmit−only mode and the bi−directional mode. There is a
separate 2−wire protocol to support each mode, each having
a separate clock input (VCLK and SCL respectively) and
both modes sharing a common bi−directional data line
(SDA). The CAT24C21 enters the transmit−only mode upon
power up and begins outputting data on the SDA pin with
each clock signal on the VCLK pin. The device will remain
in the transmit−only mode until there is a valid HIGH to
LOW transition on the SCL pin, when it will switch to the
bi−directional mode (Figure 2). Once in the bi−directional
mode, the only way to return to the transmit−only mode is
by powering down the device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit−only mode. When held low,
in bi−directional mode, it will inhibit write operations.


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