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AD9559PCBZ 数据表(PDF) 6 Page - Analog Devices

部件名 AD9559PCBZ
功能描述  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
Download  120 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9559PCBZ 数据表(HTML) 6 Page - Analog Devices

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AD9559
Data Sheet
Rev. 0 | Page 6 of 120
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CRYSTAL RESONATOR PATH
Crystal Resonator Frequency Range
10
50
MHz
Fundamental mode, AT cut crystal
Maximum Crystal Motional Resistance
100
REFERENCE INPUTS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIFFERENTIAL OPERATION
Frequency Range
The reference input divide-by-2 block must be engaged
for fIN > 705 MHz
Sinusoidal Input
10
750
MHz
LVPECL Input
0.002
1250
MHz
LVDS Input
0.002
750
MHz
Minimum Input Slew Rate
40
V/μs
Minimum limit imposed for jitter performance
Common-Mode Input Voltage
AC-Coupled
1.9
2
2.1
V
Internally generated
DC-Coupled
1.0
2.4
V
Differential Input Voltage Sensitivity
mV
Minimum differential voltage across pins required to
ensure switching between logic levels; instantaneous
voltage on either pin must not exceed the supply rails
fIN < 800 MHz
240
mV
fIN = 800 MHz to 1050 MHz
320
mV
fIN = 1050 MHz to 1250 MHz
400
mV
Differential Input Voltage Hysteresis
55
100
mV
Input Resistance
21
kΩ
Input Capacitance
3
pF
Minimum Pulse Width High
LVPECL
390
ps
LVDS
640
ps
Minimum Pulse Width Low
LVPECL
390
ps
LVDS
640
ps
SINGLE-ENDED OPERATION
Frequency Range (CMOS)
0.002
300
MHz
Minimum Input Slew Rate
40
V/μs
Minimum limit imposed for jitter performance
Input Voltage High (VIH)
1.2 V to 1.5 V Threshold Setting
1.0
V
1.8 V to 2.5 V Threshold Setting
1.4
V
3.0 V to 3.3 V Threshold Setting
2.0
V
Input Voltage Low (VIL)
1.2 V to 1.5 V Threshold Setting
0.35
V
1.8 V to 2.5 V Threshold Setting
0.5
V
3.0 V to 3.3 V Threshold Setting
1.0
V
Input Resistance
47
kΩ
Input Capacitance
3
pF
Minimum Pulse Width High
1.5
ns
Minimum Pulse Width Low
1.5
ns


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