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AD9559 数据表(PDF) 1 Page - Analog Devices |
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AD9559 数据表(HTML) 1 Page - Analog Devices |
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1 / 120 page  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet AD9559 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications Dual digital PLL architecture with four reference inputs (single-ended or differential) 4x2 crosspoint allows any reference input to drive either PLL Input reference frequencies from 2 kHz to 1250 MHz Reference validation and frequency monitoring (2 ppm) Programmable input reference switchover priority 20-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs Output frequencies: 262 kHz to 1250 MHz Programmable 17-bit integer and 24-bit fractional feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 2 kHz Low noise system clock multiplier Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles Pin program function for easy frequency translation configuration Software controlled power-down 72-lead (10 mm × 10 mm) LFCSP package APPLICATIONS Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications GENERAL DESCRIPTION The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557. FUNCTIONAL BLOCK DIAGRAM REFERENCE INPUT MONITOR AND MUX STABLE SOURCE DIGITAL PLL 0 DIGITAL PLL 1 CLOCK MULTIPLIER ANALOG PLL 0 ANALOG PLL 1 ÷3 TO ÷11 HF DIVIDER 0 ÷3 TO ÷11 HF DIVIDER 1 EEPROM SERIAL INTERFACE (SPI OR I2C) STATUS AND CONTROL PINS CHANNEL 0B DIVIDER CHANNEL 0A DIVIDER CHANNEL 1A DIVIDER CHANNEL 1B DIVIDER AD9559 Figure 1. |
类似零件编号 - AD9559 |
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类似说明 - AD9559 |
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