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EP2SGX130G 数据表(PDF) 44 Page - Altera Corporation |
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EP2SGX130G 数据表(HTML) 44 Page - Altera Corporation |
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44 / 316 page  2–36 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 Transceivers Figure 2–29. EP2SGX130 Device Inter-Transceiver and Global Clock Connections Notes to Figure 2–29: (1) There are two transmitter PLLs in each transceiver block. (2) There are four receiver PLLs in each transceiver block. (3) The Global Clock line must be driven by an input pin. Transmitter PLL 0 Transceiver Block 0 REFCLK0 4 Receiver PLLs Transmitter PLL 1 REFCLK1 IQ[4..0] IQ[4..0] IQ[4..0] Global clk line To IQ0 Transmitter PLL 0 Transceiver Block 1 4 Receiver PLLs Transmitter PLL 1 IQ[4..0] IQ[4..0] IQ[4..0] To IQ1 Transmitter PLL 0 Transceiver Block 2 4 Receiver PLLs Transmitter PLL 1 IQ[4..0] IQ[4..0] IQ[4..0] To IQ4 Transmitter PLL 0 Transceiver Block 3 4 Receiver PLLs Transmitter PLL 1 IQ[4..0] IQ[4..0] IQ[4..0] To IQ2 Transmitter PLL 0 Transceiver Block 4 4 Receiver PLLs Transmitter PLL 1 From Global Clock Line (3) IQ[4..0] IQ[4..0] IQ[4..0] To IQ3 IQ[4..0] To PLD Global Clocks 16 Interface Clocks From Global Clock Line (3) ÷2 REFCLK0 ÷2 REFCLK0 ÷2 REFCLK0 ÷2 REFCLK0 ÷2 ÷2 REFCLK1 ÷2 REFCLK1 ÷2 REFCLK1 ÷2 REFCLK1 ÷2 Global clk line Global clk line Global clk line Global clk line Global clk line Global clk line Global clk line Global clk line Global clk line From Global Clock Line (3) From Global Clock Line (3) From Global Clock Line (3) From Global Clock Line (3) Transceiver Clock Generator Block Transceiver Clock Generator Block Transceiver Clock Generator Block Transceiver Clock Generator Block Transceiver Clock Generator Block |
类似零件编号 - EP2SGX130G |
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类似说明 - EP2SGX130G |
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