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EP2SGX130G 数据表(PDF) 37 Page - Altera Corporation |
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EP2SGX130G 数据表(HTML) 37 Page - Altera Corporation |
37 / 316 page Altera Corporation 2–29 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture reduce the interface speed. For example, at 6.375 Gbps, the transceiver logic has a double-byte-wide data path that runs at 318.75 MHz in a ×20 deserializer factor, which is above the maximum FPGA interface speed. When using the byte deserializer, the FPGA interface width doubles to 40-bits (36-bits when using the 8B/10B encoder) and the interface speed reduces to 159.375 MHz. Byte Ordering Block The byte ordering block shifts the byte order. A pre-programmed byte in the input data stream is detected and placed in the least significant byte of the output stream. Subsequent bytes start appearing in the byte positions following the LSB. The byte ordering block inserts the programmed PAD characters to shift the byte order pattern to the LSB. Based on the setting in the MegaWizard® Plug-In Manager, the byte ordering block can be enabled either by the rx_syncstatus signal or by the rx_enabyteord signal from the PLD. When the rx_syncstatus signal is used as enable, the byte ordering block reorders the data only for the first occurrence of the byte order pattern that is received after word alignment is completed. You must assert rx_digitalreset to perform byte ordering again. However, when the byte ordering block is controlled by rx_enabyteord, the byte ordering block can be controlled by the PLD logic dynamically. When you create your functional mode in the MegaWizard, you can select byte ordering block only if rate matcher is not selected. Receiver Phase Compensation FIFO Buffer The receiver phase compensation FIFO buffer resides in the transceiver block at the FPGA boundary and cannot be bypassed. This FIFO buffer compensates for phase differences and clock tree timing skew between the receiver clock domain within the transceiver and the receiver FPGA clock after it has transferred to the FPGA. Table 2–9. Byte Deserializer Input and Output Widths Input Data Width (Bits) Deserialized Output Data Width to the FPGA (Bits) 20 40 16 32 10 20 816 |
类似零件编号 - EP2SGX130G |
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类似说明 - EP2SGX130G |
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