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EP2SGX130G 数据表(PDF) 81 Page - Altera Corporation |
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EP2SGX130G 数据表(HTML) 81 Page - Altera Corporation |
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81 / 316 page  Altera Corporation 2–73 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture M4K RAM Blocks The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes: ■ True dual-port RAM ■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b , renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–51. |
类似零件编号 - EP2SGX130G |
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类似说明 - EP2SGX130G |
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