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EP2SGX130G 数据表(PDF) 64 Page - Altera Corporation |
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EP2SGX130G 数据表(HTML) 64 Page - Altera Corporation |
64 / 316 page 2–56 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 Adaptive Logic Modules Figure 2–41. ALM in Arithmetic Mode While operating in arithmetic mode, the ALM can support simultaneous use of the adder’s carry output along with combinational logic outputs. In this operation, the adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–42. The equation for this example is: R = (X < Y) ? Y : X To implement this function, the adder is used to subtract ‘Y’ from ‘X’. If ‘X’ is less than ‘Y’, the carry_out signal will be ‘1’. The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data ‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y’, the syncload signal is de-asserted and ‘X’ drives the data port of the registers. dataf0 datae0 carry_in carry_out dataa datab datac datad datae1 dataf1 DQ DQ To general or local routing To general or local routing reg0 reg1 To general or local routing To general or local routing 4-Input LUT 4-Input LUT 4-Input LUT 4-Input LUT adder1 adder0 |
类似零件编号 - EP2SGX130G |
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类似说明 - EP2SGX130G |
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