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EP2SGX90F 数据表(PDF) 36 Page - Altera Corporation |
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EP2SGX90F 数据表(HTML) 36 Page - Altera Corporation |
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36 / 316 page  2–28 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 Transceivers asserted. All 8B/10B control signals, such as disparity error or control detect, are pipelined with the data in the Stratix II GX receiver block and are edge aligned with the data. Figure 2–23 shows how the 20-bit code is decoded to the 16-bit data + 2-bit control indicator. Figure 2–23. 20-Bit to 16-Bit Decoding Process There are two optional error status ports available in the 8B/10B decoder, rx_errdetect and rx_disperr. These status signals are aligned with the code group in which the error occurred. Receiver State Machine The receiver state machine operates in Basic, GIGE, PCI Express, and XAUI modes. In GIGE mode, the receiver state machine replaces invalid code groups with K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group. Byte Deserializer The byte deserializer widens the transceiver data path before the FPGA interface. This reduces the rate at which the received data needs to be clocked at in the FPGA logic. The byte deserializer block is available in both single- and double-width modes. The byte deserializer converts the one- or two-byte interface into a two- or four-byte-wide data path from the transceiver to the FPGA logic (see Table 2–9). The FPGA interface has a limit of 250 MHz, so the byte deserializer is needed to widen the bus width at the FPGA interface and 19 18 17 16 15 14 13 12 11 10 Cascaded 8B/10B Conversion j1 h1 g1 f1 i1 e1 d1 c1 b1 a1 MSB LSB 15 14 13 13 11 10 9 8 H1 G1 F1 E1 D1 C1 B1 A1 CTRL[1..0] 98 76 5 4 3 2 1 0 jh g fi e d c b a 7 6 543 2 1 0 HG F E D C B A Parallel Data |
类似零件编号 - EP2SGX90F |
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类似说明 - EP2SGX90F |
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