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EP2SGX90F 数据表(PDF) 33 Page - Altera Corporation

部件名 EP2SGX90F
功能描述  Section I. Stratix II GX Device Data Sheet
Download  316 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2SGX90F 数据表(HTML) 33 Page - Altera Corporation

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Altera Corporation
2–25
October 2007
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Rate Matcher
Rate matcher is available in Basic, PCI Express, XAUI, and GIGE modes
and consists of a 20-word deep FIFO buffer and a FIFO controller.
Figure 2–20 shows the implementation of the rate matcher in the
Stratix II GX device.
Figure 2–20. Rate Matcher
In a multi-crystal environment, the rate matcher compensates for up to a
± 300-PPM difference between the source and receiver clocks. Table 2–8
shows the standards supported and the PPM for the rate matcher
tolerance.
Basic Mode
In Basic mode, you can program the skip and control pattern for rate
matching. In single-width Basic mode, there is no restriction on the
deletion of a skip character in a cluster. The rate matcher deletes the skip
characters as long as they are available. For insertion, the rate matcher
inserts skip characters such that the number of skip characters at the
output of rate matcher does not exceed five. In double-width mode, the
rate matcher deletes skip character when they appear as pairs in the
upper and lower bytes. There are no restrictions on the number of skip
characters that are deleted. The rate matcher inserts skip characters as
pairs.
Table 2–8. Rate Matcher PPM Support Note (1)
Standard
PPM
XAUI
± 100
PCI Express (PIPE)
± 300
GIGE
± 100
Basic Double-Width
± 300
Note to Table 2–8:
(1)
Refer to the Stratix II GX Transceiver User Guide for the Altera®-defined scheme.
Rate
Matcher
dataout
datain
wrclock
rdclock


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