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EP2SGX90F 数据表(PDF) 55 Page - Altera Corporation |
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EP2SGX90F 数据表(HTML) 55 Page - Altera Corporation |
55 / 316 page Altera Corporation 2–47 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture load acts as a preset when the asynchronous load data input is tied high. When the asynchronous load/preset signal is used, the labclkena0 signal is no longer available. The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack™ interconnects have inherently low skew. This low skew allows the MultiTrack interconnects to distribute clock and control signals in addition to data. Figure 2–34 shows the LAB control signal generation circuit. Figure 2–34. LAB-Wide Control Signals Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 There are two unique clock signals per LAB. |
类似零件编号 - EP2SGX90F |
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类似说明 - EP2SGX90F |
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