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EPF10K30 数据表(PDF) 58 Page - Altera Corporation |
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EPF10K30 数据表(HTML) 58 Page - Altera Corporation |
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58 / 128 page  58 Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 26. FLEX 10K Device IOE Timing Model Figure 27. FLEX 10K Device EAB Timing Model Figures 28 shows the timing model for bidirectional I/O pin timing. Data-In I/O Register Delays tIOCO tIOCOMB tIOSU tIOH tIOCLR Output Data Delay tIOD I/O Element Control Delay tIOC Input Register Delay tINREG Output Delays tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 I/O Register Feedback Delay tIOFD Input Delay tINCOMB Clock Enable Clear Data Feedback into FastTrack Interconnect Clock Output Enable EAB Data Input Delays tEABDATA1 tEABDATA2 Data-In Write Enable Input Delays tEABWE1 tEABWE2 EAB Clock Delay tEABCLK Input Register Delays tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL RAM/ROM Block Delays tAA tDD tWP tWDSU tWDH tWASU tWAH tWO Output Register Delays tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL tEABOUT Address WE Input Register Clock Output Register Clock Data-Out EAB Output Delay |
类似零件编号 - EPF10K30 |
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类似说明 - EPF10K30 |
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