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UC3844 数据表(PDF) 7 Page - Fairchild Semiconductor |
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UC3844 数据表(HTML) 7 Page - Fairchild Semiconductor |
7 / 12 page UC3842/UC3843/UC3844/UC3845 7 Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset. Figure 9. Slope Compensation A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch spikes. Temperature ( °C) Figure 10. Temperature Drift (Vref) Temperature ( °C) Figure 11. Temperature Drift (Ist) Temperature ( °C) Figure 12. Temperature Drift (Icc) UC3842/UC3843 |
类似零件编号 - UC3844 |
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类似说明 - UC3844 |
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