AD7664 datasheet(6/28 Pages) AD

部件名	AD7664

功能描述	18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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AD7674

Rev. A | Page 6 of 28

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1]

Symbol

0

1

Unit

DIVSCLK[0]

0

1

0

1

SYNC to SCLK First Edge Delay Minimum

t18

3

17

ns

Internal SCLK Period Minimum

t19

25

60

120

240

ns

Internal SCLK Period Maximum

t19

40

80

160

320

ns

Internal SCLK HIGH Minimum

t20

12

22

50

100

ns

Internal SCLK LOW Minimum

t21

7

21

49

99

ns

SDOUT Valid Setup Time Minimum

t22

4

18

ns

SDOUT Valid Hold Time Minimum

t23

2

4

30

89

ns

SCLK Last Edge to SYNC Delay Minimum

t24

3

60

140

300

ns

Busy High Width Maximum (Warp)

t28

1.75

2.5

4

7

μs

Busy High Width Maximum (Normal)

t28

2

2.75

4.25

7.25

μs

Busy High Width Maximum (Impulse)

t28

2.25

3

4.5

7.5

μs

类似零件编号 - AD7664

制造商	部件名	数据表	功能描述
Analog Devices	AD7664	392Kb / 19P	16-Bit, 570 kSPS CMOS ADC REV. 0
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类似说明 - AD7664

制造商	部件名	数据表	功能描述
Analog Devices	AD7674	1,012Kb / 28P	18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC REV. A
	AD7674	587Kb / 29P	18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC
	AD7674	1Mb / 28P	18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC REV. 0
	AD7674AST	983Kb / 28P	18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC Rev. A
	AD7679	556Kb / 28P	18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC REV. 0
	AD7678	362Kb / 28P	18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC REV. A
	AD7679	620Kb / 28P	18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC REV. A
	AD7679ASTZ	620Kb / 28P	18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC REV. A
	AD7678	437Kb / 29P	18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC
	AD7679	506Kb / 29P	18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC

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AD7664 数据表(PDF) 6 Page - Analog Devices

AD7664 数据表(HTML) 6 Page - Analog Devices

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