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PIC12F1501-I 数据表(PDF) 77 Page - Microchip Technology

部件名 PIC12F1501-I
功能描述  8-Pin Flash, 8-Bit Microcontrollers
Download  278 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

PIC12F1501-I 数据表(HTML) 77 Page - Microchip Technology

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 2011 Microchip Technology Inc.
Preliminary
DS41615A-page 77
PIC12(L)F1501
8.2
Low-Power Sleep Mode
The PIC12F1501 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC12F1501 allows the user to optimize the operating
current in Sleep, depending on the application
requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con-
figuration and stabilize.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
8.2.2
PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal Power
mode when those peripherals are enabled. The
Low-Power Sleep mode is intended for use with these
peripherals:
• Brown-Out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/Interrupt-on-change pins
• Timer1 (with external clock source)
The Complementary Waveform Generator (CWG), the
Numerically Controlled Oscillator (NCO) and the Con-
figurable Logic Cell (CLC) modules can utilize the
HFINTOSC oscillator as either a clock source or as an
input source. Under certain conditions, when the
HFINTOSC is selected for use with the CWG, NCO or
CLC modules, the HFINTOSC will remain active during
Sleep. This will have a direct effect on the Sleep mode
current.
Please refer to sections 22.5 “Operation During
Sleep”, 23.7 “Operation In Sleep” and 24.10 “Oper-
ation During Sleep” for more information.
Note:
The PIC12LF1501 does not have a con-
figurable
Low-Power
Sleep
mode.
PIC12LF1501 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD
and
I/O
voltage
than
the
PIC12F1501. See Section 25.0 “Electri-
cal Specifications” for more information.


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