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EPM7064S 数据表(PDF) 32 Page - Altera Corporation

部件名 EPM7064S
功能描述  Programmable Logic Device Family
Download  66 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7064S 数据表(HTML) 32 Page - Altera Corporation

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Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade -6
Speed Grade -7
Unit
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.4
0.5
ns
tIO
I/O input pad and buffer delay
0.4
0.5
ns
tFIN
Fast input delay
(2)
0.8
1.0
ns
tSEXP
Shared expander delay
3.5
4.0
ns
tPEXP
Parallel expander delay
0.8
0.8
ns
tLAD
Logic array delay
2.0
3.0
ns
tLAC
Logic control array delay
2.0
3.0
ns
tIOE
Internal output enable delay
(2)
2.0
ns
tOD1
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
C1 = 35 pF
2.0
2.0
ns
tOD2
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (7)
2.5
2.5
ns
tOD3
Output buffer and pad delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2)
7.0
7.0
ns
tZX1
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
C1 = 35 pF
4.0
4.0
ns
tZX2
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (7)
4.5
4.5
ns
tZX3
Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2)
9.0
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
4.0
ns
tSU
Register setup time
3.0
3.0
ns
tH
Register hold time
1.5
2.0
ns
tFSU
Register setup time of fast input
(2)
2.5
3.0
ns
tFH
Register hold time of fast input
(2)
0.5
0.5
ns
tRD
Register delay
0.8
1.0
ns
tCOMB
Combinatorial delay
0.8
1.0
ns
tIC
Array clock delay
2.5
3.0
ns
tEN
Register enable time
2.0
3.0
ns
tGLOB
Global control delay
0.8
1.0
ns
tPRE
Register preset time
2.0
2.0
ns
tCLR
Register clear time
2.0
2.0
ns
tPIA
PIA delay
0.8
1.0
ns
tLPA
Low-power adder
(8)
10.0
10.0
ns


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