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EPM7064S 数据表(PDF) 51 Page - Altera Corporation

部件名 EPM7064S
功能描述  Programmable Logic Device Family
Download  66 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7064S 数据表(HTML) 51 Page - Altera Corporation

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Altera Corporation
51
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 37 and 38 show the EPM7256S AC operating conditions.
Table 37. EPM7256S External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
tPD1
Input to non-registered output
C1 = 35 pF
7.5
10.0
15.0
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF
7.5
10.0
15.0
ns
tSU
Global clock setup time
3.9
7.0
11.0
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tFSU
Global clock setup time of fast
input
3.0
3.0
3.0
ns
tFH
Global clock hold time of fast
input
0.0
0.5
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
4.7
5.0
8.0
ns
tCH
Global clock high time
3.0
4.0
5.0
ns
tCL
Global clock low time
3.0
4.0
5.0
ns
tASU
Array clock setup time
0.8
2.0
4.0
ns
tAH
Array clock hold time
1.9
3.0
4.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
7.8
10.0
15.0
ns
tACH
Array clock high time
3.0
4.0
6.0
ns
tACL
Array clock low time
3.0
4.0
6.0
ns
tCPPW
Minimum pulse width for clear
and preset
(2)
3.0
4.0
6.0
ns
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
tCNT
Minimum global clock period
7.8
10.0
13.0
ns
fCNT
Maximum internal global clock
frequency
(4)
128.2
100.0
76.9
MHz
tACNT
Minimum array clock period
7.8
10.0
13.0
ns
fACNT
Maximum internal array clock
frequency
(4)
128.2
100.0
76.9
MHz
fMAX
Maximum clock frequency
(5)
166.7
125.0
100.0
MHz


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